The present invention relates generally to integrated circuit (IC) device fabrication and, more particularly, to deep well structures with single depth, inter-well and intra-well shallow trench isolation regions.
A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, a given semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is provided by isolation structures that employ trenches filled with an insulator material (e.g., shallow trench isolation or “STI” regions). The electrical isolation of a semiconductor device from other devices located in the same well is referred to as “intra-well” isolation. In contrast, the electrical isolation of a semiconductor device from other devices in an adjacent well (typically of the opposite polarity type, but could also be a same polarity type well of a different well bias) is referred to as “inter-well” isolation. In either case, the unintended functionality of parasitic devices, such as parasitic p-n-p or n-p-n bipolar transistors, defined by various elements of the semiconductor device and adjacent semiconductor devices, needs to be suppressed. This is typically done by placing a dielectric material, such as an STI structure, in the current paths of the elements of the parasitic devices.
However, electrical isolation between n-well and p-well regions in bulk CMOS technologies presents somewhat of a quandary. On the one hand, leakage current between n-wells and adjacent p-wells is minimized (and latchup parameters are improved) by having STI features that penetrate all the way through the bottoms of the highly doped (deep) well regions. These deep STI features force potential latchup currents deep into the substrate and separate active regions in adjacent oppositely doped wells, thus providing good inter-well isolation. On the other hand, an STI must be sufficiently shallow so that distinct devices within the same polarity well (e.g., an n-well) are not cut off from one other. That is, for intra-well isolation, the STI must be shallower than the bottom of the doped well to also achieve reasonable intra-well resistances.
Perhaps the most commonly suggested method for eliminating this quandary is to use two separate STI depths, one for inter-well isolation and another for intra-well isolation. More specifically, shallow STI (i.e., “shallow shallow trench isolation”) is used between devices within the same well for intra-well isolation, while deep STI (i.e., “deep shallow trench isolation”) is used between wells for inter-well isolation. Unfortunately, problems with this dual-depth STI approach include the cost of an additional critical STI mask and etch, as well as the difficulty in etching and filling the higher aspect ratio trenches that result (e.g., aspect ratios of >10:1 for 22 nanometer deep STI). In addition, the lateral scattering and diffusion of deep well dopants, typically added to wells via high-energy implants, as well as potential misalignment of masks used to define the well's positions may also limit the minimum n+ to p+ spacing to much wider dimensions than are compatible with aggressively scaled SRAM (and other circuit device) features.